In computer science, dynamic memory allocation is the allocation of memory storage for use in a computer program during the runtime of that program. It is a way of distributing ownership of limited memory resources among many pieces of data and code. Importantly, the amount of memory allocated is determined by the program at the time of allocation and need not be known in advance. A dynamic allocation exists until it is explicitly released, either by the programmer or by a garbage collector; this is notably different from automatic and static memory allocation, which require advance knowledge of the required amount of memory and have a fixed duration. It is said that an object so allocated has dynamic lifetime.
INPUT/OUTPUT PORTS
Input-output ports have a very specific behavior concerning data memory allocation in the executive generated by SynDEx. For any application, SynDEx makes data buffer allocations for (and only for) the output ports of the atomic references of your algorithm graph. Input-output ports do not cause an allocation but instead an alias on the output port of the predecessor of this input-output port. The operation containing this input-output port directly modifies the value of its predecessor port (side-effect). This is useful to avoid reallocation of big data buffers of the same type (for instances images), by making successive computations on the same data buffer. However, as side-effects are not supposed to happen in data-flow graphs, this comes with some restrictions:
ports of delay definitions cannot be input/output ports
ports of hierarchical definitions cannot be input/output ports the data of an input/output port cannot be diffused: if we have a dependence A.o -> B.io (where A.o is an output port and B.io is an input/output port), neither A.o nor B.io can be diffused
INTERNAL REGISTERS
Members of an organization’s internal register are full time staff members of the organization, who normally work on non-emergency programmies. They have to have the agreement of their manager to be on the register.
Register members receive special training to prepare them for deployments. They are expected to make themselves available for a certain amount of time each year while they remain on the register. They can be deployed very rapidly.
They are deployed for a maximum period, which has been agreed in advance with their manager. After a deployment, they return to their previous post.
INTERRUPT VECTOR
An interrupt vector is the memory address of an interrupt handler, or an index into an array called an interrupt vector table or dispatch table. Interrupt vector tables contain the memory addresses of interrupt handlers. When an interrupt is generated, the processor saves its execution state via a context switch, and begins execution of the interrupt handler at the interrupt vector.
For more information, see the entry for interrupt.
BIOS
BIOS (pronounced [ˈbaɪoʊs]), in computing, stands for Basic Input/Output System.[1] [2]
The term is incorrectly known as Binary Input/Output System, Basic Integrated Operating System and occasionally Built In Operating System for example in Neal Stephenson's novel Snow Crash[1].
BIOS refers to the firmware code run by an IBM compatible PC when first powered on. The primary function of the BIOS is to prepare the machine so other software programs stored on various media (such as hard drives, floppies, and CDs) can load, execute, and assume control of the PC[3]. This process is known as booting up.
BIOS can also be said to be a coded program embedded on a chip that recognizes and controls various devices that make up the PC. The term BIOS is specific to personal computer vendors. Among other classes of computers, the generic terms boot monitor, boot loader or boot ROM are commonly used. Boot is short for bootstrapping.
The term first appeared in the CP/M operating system, describing the part of CP/M loaded during boot time that interfaced directly with the hardware (CP/M machines usually had a simple boot loader in ROM, and nothing else). Most versions of DOS have a file called "IBMBIO.COM" or "IO.SYS" that is analogous to the CP/M disk BIOS.
DOS (from Disk Operating System) commonly refers to the family of closely related operating systems which dominated the IBM PC compatible market between 1981 and 1995 (or until about 2000, if Windows 9x systems are included): DR-DOS, FreeDOS, MS-DOS, Novell-DOS, OpenDOS, PC-DOS, PTS-DOS, ROM-DOS and several others. They are single user, single task systems. MS-DOS from Microsoft was the most widely used. These operating systems ran on IBM PC type hardware using the Intel x86 CPUs or their compatible cousins from other makers. MS-DOS, inspired by CP/M, is still common today and was the foundation for many of Microsoft's operating systems (from Windows 1.0 through Windows Me). MS-DOS was later abandoned as the foundation for their operating systems.
INSTRUCTION SETS
An instruction set is (a list of) all instructions, and all their variations, that a processor can execute.
Instructions include:
arithmetic such as add and subtract
logic instructions such as and, or, and not
data instructions such as move, input, output, load, and store
control flow instructions such as goto, if ... goto, call, and return.
An instruction set, or instruction set architecture (ISA), is the part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O. An ISA includes a specification of the set of opcodes (machine language), the native commands implemented by a particular CPU design.
Instruction set architecture is distinguished from the microarchitecture, which is the set of processor design techniques used to implement the instruction set. Computers with different microarchitectures can share a common instruction set. For example, the Intel Pentium and the AMD Athlon implement nearly identical versions of the x86 instruction set, but have radically different internal designs.
This concept can be extended to unique ISAs like TIMI (Technology-Independent Machine Interface) present in the IBM System/38 and IBM AS/400. TIMI is an ISA that is implemented as low-level software and functionally resembles what is now referred to as a virtual machine. It was designed to increase the longevity of the platform and applications written for it, allowing the entire platform to be moved to very different hardware without having to modify any software except that which comprises TIMI itself. This allowed IBM to move the AS/400 platform from an older CISC architecture to the newer POWER architecture without having to rewrite any parts of the OS or software associated with it.
DATA TRANSFER INSTRUCTION
When stored in memory the bytes, words, and doublewords in the packed data types are stored in consecutive addresses, with the least significant byte, word, or doubleword being stored in the lowest address and the more significant bytes, words, or doubleword being stored at consecutively higher addresses. The ordering of bytes, words, or doublewords in memory is always little endian: the bytes with the lower addresses are less significant than the bytes with the higher addresses.
BRANCH INSTRUCTIONS
a branch instruction, can be taken or not taken: if a branch is not taken, the flow of control is unchanged and the next instruction to be executed is the instruction immediately following the current instruction in memory; if taken, the next instruction to be executed is an instruction at some other place in memory. There are two usual forms of branch instruction: a conditional branch that can be either taken or not taken, depending on a condition such as a CPU flag, and an unconditional branch which is always taken.
CONDITIONAL AND UNCONDITIONAL JUMPS
Conditional and Unconditional Jumps
Introduction
So far, we've only considered instructions that do computations, or data movement (i.e., load and store).
You can do straight-line code with these instructions. However, high level languages must be able to handle conditional statements and loops.
ISAs do not have support for block programming, nor support for traditional loops. Instead, they have support for conditional and unconditional jumps, which are essentially goto statements.
What does it mean to jump?
Perhaps you've never given much thought to it, but have you thought about what it means for the control flow of a program to "jump". Do you recall what your teacher said when you learned how an if-else statement worked? Perhaps the teacher pointed out that if a condition was true, then the control flow went into the if-body, and if the condition was false, the control flow went into the else-body.
This was probably demonstrated by pointing at some code on a board or a power point slide, or perhaps by using a debugger.
However, those jumps have to be implemented, and "jumping" is too abstract a concept.
Here's what happens. At any point in time, you are executing some instruction. This instruction appears in memory at some address. The hidden register PC (the program counter) stores the address of the instruction that's currently being executed.
When a conditional jump occurs, a condition is checked. If the condition is true, then the jump occurs. A jump means updating the PC with the instruction to execute, which in turn causes that instruction to be fetched and run. If the condition is false, then the instruction at PC + 4 is executed. PC + 4 is the address of the next instruction in memory. We add 4 instead of 1 because each address in memory stores one byte and each MIPS instruction requires four bytes of memory.
An unconditional jump always occurs. There is no conditions to check.
A conditional jump is called a branch in MIPS.
Jump instructions
We'll consider several jump instructions, and also talk about slt, which is used to implement certain branches that don't exist as instructions MIPS.
There are the list of instructions we'll look at.
beq Branches if the quantities of two registers are equal.
bne Branches if the quantities of two registers are NOT equal.
bgtz Branches if a quantity in a register is greater than zero (quantity is 32 bit, 2C).
bgez Branches if a quantity in a register is greater than or equal to zero (quantity is 32 bit, 2C).
bltz Branches if a quantity in a register is less than zero (quantity is 32 bit, 2C).
blez Branches if a quantity in a register is less than or equal to zero (quantity is 32 bit, 2C).
j Jump to an address
jr Jump to an address stored in a register
jal Jump to an address, and store the return address in a register.
jalr Jump to an address stored in a register, and store the return address in another register.
Here's how they would be written beq $rs, $rt, offsetbne $rs, $rt, offsetbgez $rs, offsetbgtz $rs, offsetblez $rs, offsetbltz $rs, offsetj offsetjal offsetjr $rsjalr $rs
The offset is a 16-bit 2C value, except for j and jal, where they are 26 bits UB. j and jal are J-type instructions, while all the branch instructions are I-type. Notice that the instruction format (e.g., R-type, I-type) are formats. Just because an instruction is used for jumping (e.g., beq) does not mean it's a J-type instruction. It's the format that matters.
Semantics of Branch instructions
The branch instructions (i.e., beq, bne, bgtz, bgez, bltz, blez) all have 16 bit immediate values.
How are these values used to compute the address to jump (should the condition be true)? Addr = PC + (IR15)14 IR15-0 00 if ( condition ) PC <- Addr else PC <- PC + 4 You don't want to use the 16 bit immediate value as an address to jump to because that limits where you can jump. MIPS has 32 bits for an address. If you only use 16 bits, you are using a very small fraction of the possible addresses. To think about a reasonable solution, ask yourself when a branch occurs in a program? They occur in loops and conditional statements. Most loops and conditional statements occur within a few statements in the code. Even if you expect that each C statement may translate into 20 or more MIPS instructions, jumps are expected to jump within several thousand instructions of the jump instruction. Therefore, it makes sense to jump relative to the current instruction. This kind of jumping is called PC relative addressing because it adds an offset to the program counter. If we do this naively, we can jump anywhere from PC - 215 to PC + 215 - 1, which is the range of values for a 16 bit 2C. However, that is naive. Instructions are 32 bits long. Thus, they are 4-byte quantities. In MIPS, 4-byte quantities must be stored at word-aligned addresses, which means those addresses must be divisible by 4. This means that we will never jump to an address that is not divisible by 4. Thus, three-fourths of all immediate values would be useless (only one-fourth of the immediate values end in 00, the other three-fourths end in 01, 10, or 11). The better idea is to realize that we want to jump to an address divisible by 4, and not store the 00 in the immediate value. This is a similar idea to the "hidden 1" used in floating point. Just think of this as the "hidden 00". In effect, the immediate value tells you how many instructions to jump forward or backwards. To compute the address of the branch instruction, take the 16 bit immediate value, and sign-extend it. Then shift it left by 2 bits (which fills in 0's for the low 2 bits). The result allows you to jump four times as far. You can jump anywhere from PC - 217 to PC + 217 - 4. Notice we subtract 4, because we multiplied the limits of the 16-bit 2C value by 4 (the limits of a 16-bit 2C values are -215 up to 215 - 1). Semantics of Jump instructions Both j and jal are J-type instructions. J-type instructions use 6 bits for the opcode, and 26 bits for the immediate value (called the target). This is the semantics of the j instruction. PC <- PC31-28 IR25-0 00 The new address is computed by taking the upper 4 bits of the PC, concatenated to the 26 bit immediate value, and the lower two bits are 00, so the address created remains word-aligned. This is called pseudo-direct addressing. Direct addressing would specify are 32 bits. It's called pseudo-direct because some bits of the PC are used to compute the address. j allows you to access 1/16 of all possible word-aligned addresses. jal and subroutines The semantics of jal are similar, except the return address is stored. R[31] <- PC + 4 PC <- PC31-28::IR25-0::00 Notice register 31 is assigned PC + 4. What is PC + 4? If PC is the current instruction, then PC + 4 is the next instruction. jal is used for subroutine calls. In a subroutine call, you jump to a subroutine (basically, it's a function call). When you are done, the subroutine jumps back to the instruction just after the subroutine call. In MIPS, jal are used for subroutine calls. How do you get back after the subroutine call? You need to store the return address. This return address is PC + 4, and is stored in $r31. When the subroutine call is finished, you run the instruction jr $r31, which causes the PC to be assigned the address in $r31. That causes the control flow to return to the instruction just after the return call. CISC processors often have very few registers. Instead of storing the return address in a register, the return address was often stored on the stack, in memory. Storing it in a register has the advantage that it's quick. Memory is much slower by comparison. Of course, you may wonder what happens if a jal call is made while in a subroutine. Won't the return address be overwritten with a new return address? That's true. In this case, you must place the return address onto the stack. Using the register helps delay the use of the stack, somewhat. If you have many leaf procedures (functions/subroutines that do not call any other subroutines), then saving the return address in a register offers speed improvements. It's Really PC + 8 It turns out that the return address is PC + 8, not PC + 4. This is most likely due to the fact that jump instructions have to be followed by a branch delay slot instruction. Such instructions are often placed after jumps and branches for the purposes of avoiding stalling in pipelines. Since pipelining is an advanced topic, we'll assume the return address is PC + 4.. Jumping to Arbitrary Word-Aligned Addresses Even though j and jal are both useful, they still don't allow you to access all possible word-aligned addresses. You need instructions that let you do this. So there is jr and jalr. Instead of specifying the address to jump to in the instruction, you refer to a register, which specifies the entire 32 bit instruction. Since registers have to be specified, jr and jalr are not J-type instructions. They are R-type. This is unusual because they could be I-type. However, by making them R-type, you can use more of the function bits. The semantics of jr $rs is: PC <- R[s] The semantics of jalr $rs is: R[31] <- PC + 4 PC <- R[s] Branch Instructions and Labels Consider the following set of instructions: beq $r1, $r2, L1 # (0) If R[1] == R[2] goto L1 addi $r1, $r1, 1 # (1) R[1]++ addi $r2, $r2, 1 # (2) R[2]++L1: add $r1, $r1, $r2 # (3) R[1] = R[1] + R[2] L1 is a label. Labels refer to addresses. These addresses are computed by the assembler. An assembler is a program that converts an assembly language code to machine code. Labels make it easier for the ISA programmer to write programs. That way, they don't have to compute the offsets. The assembler computes the offset in the following way. Instead of using the current instruction, it computes target instruction - (branch instruction + 1). For example, let branch instruction be instruction 0 (it's in parentheses in the comments above). The target instruction is where L1 appears. It's at instruction 3. So, subtract 3 - 1 = 2. The offset is +2. The same rule applies even if you branch backwards. L1: add $r1, $r1, $r2 # (0) R[1] = R[1] + R[2] addi $r1, $r1, 1 # (1) R[1]++ addi $r2, $r2, 1 # (2) R[2]++ beq $r1, $r2, L1 # (3) If R[1] == R[2] goto L1 In this case, the branch instruction is instruction 3. The target instruction (where L1 is) is instruction 0. So (0 - (3 + 1)) = -4. The offset is -4. This would be converted to 16 bit 2C, and stored in the immediate part of the instruction. You might wonder why compute branch instruction + 1. Why not just the branch instruction? Once the instruction is fetched, PC is often incremented to PC + 4, the next instruction in memory, in anticipation of the next instruction to be fetched. So, it's easier to do the computation with PC + 4 (which is the same as branch instruction + 1). You may also wonder how I numbered the instructions. How did I decide a certain instruction was instruction 0? It turns out it doesn't matter. Pick any number you want: L1: add $r1, $r1, $r2 # (21) R[1] = R[1] + R[2] addi $r1, $r1, 1 # (22) R[1]++ addi $r2, $r2, 1 # (23) R[2]++ beq $r1, $r2, L1 # (24) If R[1] == R[2] goto L1 Instead of making the first instruction, instruction 0, I made it instruction 21. If you do the computations, you get (21 - (24 + 1)) = -4. Recall these computations compute differences, and so as long as the instructions are numbered in ascending order, you get the same result, regardless of what instruction number you start with. This kind of address computation is called PC-relative since it is computed based on the value of PC, the program counter. Jump Instructions and Labels Jump instructions also jump to labels (at least, j and jal). The assembler also figures out the appropriate addresses. However, it does so using pseudo-direct addressing. Pseudo-direct addressing has one disadvantage compared to PC-relative addressing. It's harder to relocate the code. Relocating the code means to place code at a different address in memory. Typically, a loader program would have to rewrite instructions that use direct addressing because the instruction it jumps to might not be in a particular location in memory (since the program has been relocated). This is similar to informing various institutions that you have moved. You tell them the new address so they don't mail you stuff to your old address. Similarly, if a program is loaded at a different address than the assembler expected, then instructions like j and jal, which are pseudo-direct may need to be updated. PC-relative instructions like beq do not need this, since relative addressing works at any location in memory. These days, with virtual memory, it's not so necessary to relocate code. Virtual memory will be covered at some future set of notes. Machine Code Representation Branch instructions are I-type. Instruction B31-26 B25-21 B20-16 B15-0 opcode register s register t immediate beq $rt, $rs,
000 100
-
-
offset
bne $rt, $rs,
000 101
-
-
offset
bgtz $rs,
000 111
-
00000
offset
bgez $rs,
000 001 (REGIMM)
-
00001 (BGEZ)
offset
bltz $rs,
000 001 (REGIMM)
-
00000 (BLTZ)
offset
blez $rs,
000 110
-
00000
offset
The dashes are 5-bit encoding of the register number in UB. For example, $r7 is encoded as 00111. The offset is represented in 16-bit 2C.
If you look at bgtz, bgez, bltz, and blez, they're all unusual. For example, bgtz and blez are I-type instructions, where B20-16, which are the bits normally used by $rt, are all 0's (otherwise the instruction is invalid).
bltz and bgez use a special 000 001 opcode for register immediate. For this unsual use of I-type instructions, bits B20-16, which are the bits normally used by $rt, are used like the function bits in R-type instructions.
jr and jalr are R-type instructions.
Instruction
B31-26
B25-21
B20-16
B15-11
B10-6
B5-0
opcode
register s
register t
register d
shift amount
function
jr $rs
000 000 (SPECIAL)
-
00000
00000
00000
001 000
jalr $rs
000 000 (SPECIAL)
-
00000
11111
00000
100 010
You will notice that bits B15-11 are set to all 1's, which refers to register 31. As it turns out, jalr can take an optional second argument, where you specify the return address register. When it's not specified, the assembler fills in 11111 into those bits. This option is not available for jr (since no return addresses are used).
Finally, both j and jal are J-type instructions.
Instruction
B31-26
B25-0
opcode
target
j
000 010
-
jal
000 011
-
The dashes are the 26-bit target, which uses pseudo-direct addressing.
LOOPING INSTRUCTIONS
1. A method of processing loop instructions using a data processing device having a central processing unit (CPU) and a coprocessor, wherein the CPU fetches and predecodes instructions retrieved from program memory and determines whether the instructions are CPU-type or coprocessor-type, comprising the steps of: decoding the coprocessor-type instructions by the coprocessor and if a loop operation is decoded, retrieving from the program memory the instructions within the loop; storing the retrieved instructions within the loop in a loop buffer: executing at least one coprocessor-type instruction from the loop buffer by the coprocessor, and forwarding any CPU-type instructions from the loop buffer to the CPU for execution; and inhibiting instruction fetch from the program memory while instructions within the loop are executed in a subsequent iteration of the loop. 2. The method of claim 1, further including the step of accessing the instructions within the loop from the loop buffer in a subsequent iteration of the loop. 3. The method of claim 1, further including determining a backward branch distance for use by the CPU to control branching to and from the loop. 4. The method of claim 1 further including the steps of: determining from the loop instruction a number of iterations of the loop operation; decrementing by the coprocessor the number of iterations upon completion of each loop; and signaling to the CPU the completion of the loop operation when reaching the end of the number of iterations. 5. The method of claim 1, wherein said storing step includes storing 'n' loop instructions in 'm' registers of the loop buffer and addressing the 'm' registers by log2m in least significant bits (LSBs) of a program counter which is also used for addressing the program memory, wherein n or m is any natural number and n is less than or equal to m. 6. The method of claim 5, further including the steps of accessing the instructions stored in the loop buffer through a multiplexer and controlling the multiplexer output by the log2m LSBs of the program counter. 7. The method of claim 5, wherein a first instruction within the loop is stored in one of the m registers addressed by the LSBs of the program counter. 8. The method of claim 1, further including the steps of signaling the presence or absence of an active loop instruction by a loop buffer flag in each of the 'm' registers in the loop buffer, the presence of an active instruction in a register is indicated by a preassigned signal in the loop buffer flag. 9. The method of claim 8, further including the step of accessing each flag in the loop buffer by log2m least significant bits of a program counter used for addressing the program memory. 10. The method of claim 8, further including the step of multiplexing an instruction from the loop buffer and the program memory, the multiplexing is dependent upon a presence of an active instruction signal from a loop buffer flag. 11. The method of claim 8, wherein said step of inhibiting instruction fetch from the program memory includes sending an inhibit signal to the program memory when the preassigned signal in the loop buffer flag is read and indicates the presence of an active loop instruction. 12. The method of claim 11, wherein the preassigned signal in each of said loop buffers is selectively alterable by the CPU independent of the presence or absence of an active instruction in corresponding registers. 13. The method of claim 8, further including the step of clearing the loop buffer flag when the loop operation is completed. 14. A data processing device comprising: a central processing unit (CPU) for fetching instructions from a program memory, predecoding the instructions and sending a signal (CCLK) to a coprocessor if a coprocessor-type instruction is decoded; a coprocessor for decoding the coprocessor-type instructions upon receipt of the signal (CCLK); and a loop buffer for receiving from the program memory instructions within a loop and storing the instructions within the loop when the coprocessor decodes a loop operation from the coprocessor-type instructions, wherein the instructions within the loop are retrieved from the loop buffer for execution in a subsequent iteration of the loop, and wherein the loop buffer instructions of coprocessor-type are executed by the coprocessor and the loop buffer instructions of CPU-type are forwarded to the CPU for execution. 15. The device of claim 14, wherein a disable signal is sent to the program memory for inhibiting access of the program memory while the instructions within the loop are retrieved from the loop buffer. 16. The device of claim 14, wherein the loop buffer includes 'm' registers, each having a corresponding loop buffer flag for indicating whether the corresponding register is filled with an instruction. 17. The device of claim 16, wherein the loop buffer flags are accessed by log2m least significant bits of a program counter used for addressing the program memory. 18. The device of claim 16, wherein a program memory inhibit signal is generated based on a signal read from the loop buffer flag. 19. The device of claim 14, wherein the loop buffer includes 'm' registers and the registers are addressed by log2m LSBs of a program counter used for addressing the program memory. 20. The device of claim 16, further including a multiplexer for multiplexing between the instructions retrieved from the program memory and the instructions retrieved from the loop buffer, the multiplexor being controlled by signals read from the loop buffer flags. 21. The device of claim 14, wherein the coprocessor decodes from a loop instruction a loop block size and a number of iterations of looping, and calculates a backward branch distance for use by the CPU to control branching to and from the loop. 22. The device of claim 21, wherein the backward branch distance is the loop block size minus one. 23. A data processing device comprising: a central processing unit (CPU) for fetching instructions from a program memory, predecoding the instructions and sending a signal (CCLK) to a coprocessor if a coprocessor-type instruction is decoded; a coprocessor for decoding the coprocessor-type instructions upon receipt of the signal (CCLK); and a loop buffer for receiving from the program memory instructions within a loop and storing the instructions within the loop when the coprocessor decodes a loop operation from the coprocessor-type instructions, wherein the instructions within the loop are retrieved from the loop buffer for execution in a subsequent iteration of the loop, wherein the loop buffer instructions of coprocessor-type are executed by the coprocessor and the loop buffer instructions of CPU-type are forwarded to the CPU for execution, and wherein a disable signal is sent to the program memory for inhibiting access of the program memory while the instructions within the loop are retrieved from the loop buffer.
ARITHMETIC INSTRUCTIONS
ARITHMETIC INSTRUTIONS
Add
Mnemonic
A
Description
The basic purpose of this instruction is to add two 16-bit operands. One of the operands must first be loaded into the accumulator, such as by means of execution of a load-accumulator instruction. The add instruction then provides the address of the other operand, which must be in main storage. Addition takes place, and the result is placed in the accumulator:
(Sign bit 0 = 0 specifies + number.) 0 000 0000 1001 1101 = Contents of accumulator+0 000 0010 0011 0101 = Contents of storage location addressed by add instruction 0 000 0010 1101 0010 = Result loaded into accumulator
Although the result replaces the contents of the accumulator, the contents of the addressed storage location remain unchanged.
The result of the addition is either positive or negative, depending upon the magnitude of the values used and whether the signs of the two operands are the same:
+ plus a + = + - plus a - = - + plus a - = sign of the larger operand - plus a + = sign of the larger operand
The value in the accumulator is positive if the leftmost bit is at a value of 0; the value in the accumulator is negative if the leftmost bit is at a value of 1. Negative numbers are in two's-complement form.
There are no addressing exceptions for the add instruction; all forms of addressing that are described under "Effective-Address Generation" apply to the A instruction.
Indicators: The carry indicator is automatically reset to 0 at the beginning of an add-instruction execution. If, during the add-instruction execution, a carry-out of the high-order (leftmost) position of the accumulator occurs, then the carry indicator is set to 1; if no such carry-out of the high-order position occurs, the carry indicator remains at its reset condition of 0. It can subsequently be set or reset by the various actions listed under "Carry and Overflow Indicators" (see Figure 13).
The overflow indicator must be reset to 0 if it is to be used during execution of an add instruction. If the overflow indicator is at a value of 1 at the start of an add operation, it is not changed regardless of the result of the add operation. If the overflow indicator is at a value of zero at the start of an add operation, it is set to a value of 1 if the addition produces a result that exceeds the capacity of the accumulator. For example, when the following two 16-bit operands are added together, S 0 100 0000 0000 0000 Operand in accumulator -- a positive number+0 100 0000 0000 0000 Operand in main storage -- a positive number 1 000 0000 0000 0000 = Result in accumulator -- a negative number(S = Sign bit)
the result is greater than the capacity of the accumulator because the accumulator specifies a negative result (the leftmost bit is at a value of 1). In this case, the overflow indicator is set to 1. The carry indicator, however, is not set to one because a carry-out of the high-order position of the accumulator does not occur. Refer to "Carry and Overflow Indicators" for a discussion of how these two indicators can be used together in certain arithmetic operations.
The maximum capacity of the accumulator is:
Power-of-2 Notation
Decimal Notation
Hexadecimal Notation
+215-1
+32,767
+7FFF
-215
-32,768
-8000
Examples
Add
Assembler Language Coding
Hexadecimal Value
Description of Instruction
Label
Operation
F
T
21
25
27
30
32
33
35..40..
A
DISP
80XX
Add contents of CSL at EA (I+DISP) to A
A
1
DISP
81XX
Add contents of CSL at EA (XR1+DISP) to A
A
2
DISP
82XX
Add contents of CSL at EA (XR2+DISP) to A
A
3
DISP
83XX
Add contents of CSL at EA (XR3+DISP) to A
A
L
ADDR
8400XXXX
Add contents of CSL at EA (Addr) to A
A
L
1
ADDR
8500XXXX
Add contents of CSL at EA (Addr+XR1) to A
A
L
2
ADDR
8600XXXX
Add contents of CSL at EA (Addr+XR2) to A
A
L
3
ADDR
8700XXXX
Add contents of CSL at EA (Addr+XR3) to A
A
I
ADDR
8480XXXX
Add contents of CSL at EA (V in CSL at Addr) to A
A
I
1
ADDR
8580XXXX
Add contents of CSL at EA (V in CSL at "Addr+XR1") to A
A
I
2
ADDR
8680XXXX
Add contents of CSL at EA (V in CSL at "Addr+XR2") to A
A
I
3
ADDR
8780XXXX
Add contents of CSL at EA (V in CSL at "Addr+XR3") to A
1 comment:
did you cut this info from any book?
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